Yes and pipeline consists of multiple frames if you look a little farther out. I think 3 separate posts pointed it out in this thread and all 3 got ignored - interleaving work with next frame has been common-place for most of this decade (give or take) and if you have an 'ideal' scenario where hypothetical hw-runs completely independent (as NVidia claimed) - you get 100% parallelism out of it, which would make the cost of ML portion for DLSS equal to 0. There's also a number of ways how that could work within single frame - but the point is it doesn't really have to.
The contended point is apparently NVidia wasn't entirely honest on what the hw can actually do, or at least so it seems.
Of course you can. And many, many reconstructed games do exactly that, a lot (sometimes all) of their PP runs before reconstruction, not after. And we see evidence of that in DLSS games as well.And you cant apply post processing without first upscaling the frame.
This isn't really efficiency question so much as misleading the public (if tensor cores indeed can only execute serially to the rest of GPU).The public doesnt really care about how efficient the use of the silicon is.