I don't know about that, the controller does have a pretty strong custom arbitration scheme over NVMe standard, and also relies on 12x R/W channels whereas a Phison controller tomorrow only goes up to 8x channels and half the priority levels, even though it is 7GB/s. That's where I would draw the line on pure bandwidth comparisons only, because their drive still probably would stay ahead in actual scenarios (not 100% sequential R/W). However the higher the peak bandwidth on the other drive the less loading times and new installs or updates. Which is good. I'm still unsure on the actual impact on the I/O hardware, because it does get impacted by clock frequency, unless they offloaded 100% of the traffic on the coprocessors, and the DMA controller might run at 1750MHz anyway. From what I understand, the decompressor is more or less repurposed AVX-256 logic from 8/9 Zen2 cores, I'm unsure if it runs a fixed clock or not. There might be a clock domain for the I/O unit as a whole anyway.
Yes, I'm interested to know more about that github part, I'm not too familiar with it. However, there might still be uncertainty on the process node used because some people had access to stolen IPs and said otherwise, but it also could be made up. But I think it's fair to say the monolithic chip approach should definitely improve the critical path so I'm very curious to see how much fabric clocks can take.
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