Correct me if I'm wrong, but the rumors suggest 16GB GDDR6 memory. To achieve that there are two options: a 256-bit bus with 2GB chips, or a 512-bit bus with 1GB chips. That's either 72 or 144mm^2. The rumor also specifies 96 ROPs, which is 32 less than present in four full SE frontends. They must be subtracted out, leaving 109.9mm^2 for frontends and the GPU common core. It seems to me that core might need to be bigger for such a large chip, though, with a more parallel scheduler, more ACES, etc. If I'm incorrect here let me know, but this may add back 7.8mm^2. Finally there's the I/O, which I assume will remain unchanged at 40.7mm^2.
All together, the total chip area without any WGPs is between 222.6 and 302.4mm^2, depending mostly on memory interface but also on the core. WIth a final chip size of 505mm^2, that leaves between 202.6 and 282.4mm^2 occupied by WGPs. Of which there would be 40 for an 80CU part. That equates to somewhere between 5.1 and 7.1mm^2 per WGP, or anywhere from 23.5% to 72.2% bigger than the corresponding 5700 WGPs. I can't conceive of any way that RT support, or even added ML cores, could raise CU size so dramatically as the high end. I think it's therefore pretty safe to say that "Big Navi" will have a 512-bit memory bus.
Even so, this leaves pretty big WGPs. A 23.5% growth would put the GitHub-configured XSX above even the biggest estimates of the total die size. Rather than 394mm^2, a 2SE 60CU/56active chip with 320-bit bus would end up at 414mm^2. (A 256-bit "Big Navi" would put XSX at 474mm^2, another strike in favor of 512-bit bus.)
Could we get the RDNA2 WGP smaller? After all, RT plus improved tensor cores only adds ~20% on the Nvidia side. Well, I presume 80CU Navi is a full chip with a binning process for a 72CU variant to maintain yields. But if it's an insular offering with no binning, it could have 44 WGPs to allow deactivation. That'd bring each down to 4.6mm^2, pretty close to the 4.4mm^2 I estimated for an 8% RT increase.
I think that's pretty unlikely to be the case. But there are all sorts of changes to cache amounts which could alter the number. Even just bumping ROPs from 96 to 128 would bring the WGP growth factor down to 18.5%.
tl;dr
- If "Big Navi" has 16GB GDDR6 as rumored, I predict it'll have a 512-bit bus, as rare as that is
- The rumored chip size does suggest the new hardware features are raising the CU size more than previously projected
- This new growth factor is enough that it calls the assumed configuration of XSX into question
* Maybe the XSX CUs don't have all RDNA2 features
* Maybe XSX has fewer CUs overall than we thought
* But maybe other hardware changes make up the difference, and XSX is exactly as believed.
P.S. We don't know the actual size of the PS5 APU. But it can be pointed out that a 40CU version a la GitHub could have the larger WGPs and still be 15%+ smaller than the XSX chip size with the original smaller ones. This opens the possibility that PS5 might have fewer but more sophisticated CUs, like PS4 Pro did versus the Xbox One X.
