Question to the known devs in here about RT:
I'm curious, do you expect RT to play a big role in next-gen console games?
Or are we still likely to see baked lighting and more novel approximations be prevalent?
cc
Locuza,
40KAl,
Fafalada
I'm just a layman not a dev.
But I think every answer from today's standpoint will be vague even if you are asking a dev.
I expect rather limited integration of ray tracing and see the current Geforce RTX hardware as a usable reference point.
I can't imagine AMD launching Epyc 2 without AVX512 and, since those would be basically Zen 2 modules, I'd imagine the design is able to support it, so it would be a matter of downporting the feature.
If they do launch Epyc 2 without AVX512 then damn, wtf AMD?
Vector maths can massively speed up some common coding structures (i.e. loops), and AVX512 can handle really wide loops, so it would be a massive boost to code execution on the CPU. Besides that, there's a bunch of speculative uses for CPU vector maths, from pathfinding and AI to RT. It's less about new things (and I'm not well versed in this enough to be able to imagine new things nonetheless) and more about making current thing much, much faster (so you can imagine more of them and better).
There is no AVX512 support in Zen 2.
AMD kept it simple and made an upgrade from 128-Bit pipes to 256-Bit.
They use relatively lightweight cores and more of them.
For multithreaded applications you still get good vector performance.
I dunno why they've decided to call CUs what is essentially half of a multiprocessor - and call the last one Work Group Processor. But yeah, there's 10 WGPs in Navi 10, each comprised of two "CUs". One could argue that WGP is actually a new CU in RDNA as it mostly fits the same requirement as a CU did in GCN.
[...] We don't know really. Looking at
this you could argue that one RDNA SIMD is able to do what you're describing as "CU" as each of them have its own scheduler now. The fact that two of RDNA "CUs" share caches and LDS mean more than what unit is able to fetch/decode/etc. It's clear that AMD tried to fit the new h/w into GCN metrics to make comparisons easier but I wonder if they've muddied the waters so to speak while doing so. Thus far what GCN had as a CU was basically an equivalent of NV's multiprocessor (SM, streaming multiprocessor), with RDNA this seem to change with CU being a pair of SIMDs while four of them (same as in GCN, btw) comprise a WGP (note the P there which stands for "processor" too) - which seem to suit NV's SM metrics better than RDNA's CU would.
RDNA has multiple working modes on different levels.
Wave32 or Wave64 is used depending on the workload.
Depending on the circumstances Wave32 or Wave64 is more efficient.
On a higher level a RDNA Compute Unit can still be compared to one GCN Compute Unit because under RDNA a Compute Unit can still work indepentendly.
Every Compute Unit can work on a Workgroup, which is also called CU mode, where the registers and caches are all exclusive per Compute Unit.
But it's also possible to have two Compute Units working on a Workgroup together and sharing ressources, this is called WGP (Work Group Processor) mode.